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nonvolatile, i 2 c ? - compatible 64 - position, digital potentiometer data sheet ad5258 rev. d document feedback information furnished by analog device s is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without not ice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s. a. tel: 781.329.4700 ? 2005 C 2013 analog devices, inc. all rights reserved. technical support www.analog. com f eatures nonvolatile memory maintains wiper settings 64- position digital potentiometer compact msop - 10 (3 mm 4.9 mm) i 2 c - compatible interface v logic pin provides increased interface flexibility end - to - end resistance 1 k ? , 10 k?, 50 k?, 100 k? resistance tolerance stored in eeprom (0.1% accuracy) power - on eeprom refresh time <1 ms software write protect command address decode pin ad0 and address decode pin ad1 allow four packages per bus 100- year typical data retention at 55 c wide operating temperature ? 4 0 c to +85 c 3 v to 5 v single supply applications lcd panel v com adjustment lcd panel brightness and contrast control mechanical potentiometer replacement in new designs programmable power supplies rf amplifier biasing automotive electronics adjustment ga in control and offset adjustment fiber to the home systems electronics level settings functional block dia gram s 05029-001 rdac register rdac dat a contro l command decode logic address decode logic contro l logic ad5258 i 2 c seria l inter f ace power- on reset a w b scl sda ad0 ad1 v dd v logic gnd rdac eeprom 6 6 figure 1 . block diagram 05029-002 command decode logic address decode logic contro l logic sc l sd a ad0 ad1 gnd eeprom i 2 c seria l inter f ace rdac register and leve l shifter a w b v logic v dd figure 2 . block diagram showing level shifters general des cription the ad5258 provides a compact, nonvolatile 3 mm 4.9 mm pack aged solution for 64 - position adjustment applications. the se devices perform the same electronic adjustment function as mechanical potentiometers 1 or variable resistors, but with enhanc ed resolution and solid - state reliability . the wiper settings are controllable through an i 2 c - compatible digital interface that is also used to read back the wi per register and eeprom content in addition, r esistor tolerance is stored within eeprom , providi ng an end - to - end tolerance accuracy of 0.1%. there is also a software write protection function that ensures data cannot be written to the eeprom register. a separate v logic pin delivers increased interface flexibility. for users who need multiple parts on one bus, address bit ad0 and address bit ad1 allow up to four devices on the same bus. 1 the terms digital potentiometer , vr ( variable resistor ), and rdac are used interchangeably.
ad5258 data sheet rev. d | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 revision his tory ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 timing char acteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin confi guration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 13 theory of operation ...................................................................... 14 programming the variable resistor ......................................... 14 programming the potentiometer divider ............................... 14 i 2 c interface ..................................................................................... 15 writing ......................................................................................... 15 storing/restoring ....................................................................... 15 reading ........................................................................................ 15 i 2 c byte formats ............................................................................. 16 generic interface ........................................................................ 16 write modes ................................................................................ 16 read modes ................................................................................. 17 store/restore modes .................................................................. 17 tolerance readback modes ...................................................... 18 esd protection of digital pins and resistor terminals ........ 19 power - up sequence ................................................................... 19 layout and power supply bypassing ....................................... 19 multiple devices on one bus ................................................... 19 display applications ...................................................................... 20 circuitry ...................................................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 1 /1 3 rev. c to rev. d changes to zero - scale error parameter and logic supply parameter, table 1 .............................................................................. 3 removed evaluation board section and figure 43, renumbered sequentially ...................................................................................... 19 5 / 10 re v. b to rev. c changes to storing/restoring section ......................................... 15 changes to table 7 .......................................................................... 16 changes to table 14 ........................................................................ 17 1 / 10 rev. a to rev. b changes to figure 44 ...................................................................... 20 updated outline dimensions ....................................................... 21 3 /07 rev. 0 to rev. a updated format .................................................................. universal changes to features section ............................................................ 1 cha nges to general description section ....................................... 1 changes to table 4 ............................................................................. 7 changes to i 2 c interface section .................................................. 15 changes to table 5 .......................................................................... 16 changes to multiple devices on one bus section ..................... 19 3/05 revision 0: initial version
data sheet ad5258 rev. d | page 3 of 24 specifications electrical character istics v dd = v l ogic = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +85c, unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity r - dnl r wb , v a = no connect lsb 1 k? ?1.5 0.3 +1.5 10 k?/50 k?/100 k? ?0.25 0.1 +0.25 resistor integral nonlinearity r - inl r wb , v a = no connect lsb 1 k? ?5 0.5 +5 10 k?/100 k? ?0.5 0.1 +0.5 50 k? ?0.25 0.1 +0.25 nominal resistor tolerance t a = 25c, v dd = 5.5 v 1 k? r ab 0.9 1.5 k? 10 k?/50 k?/100 k? r ab ?30 +30 % resistance temperature coefficient ( r ab 10 6 )/(r ab t) code = 0x00/0x20 200/15 ppm/c total wiper resistance r wb code = 0x00 75 350 ? dc characteris tics potentiometer divider mode differential nonlinearity dnl lsb 1 k? ?1 0.3 +1 10 k?/50 k?/100 k? ?0.25 0.1 +0.25 integral nonlinearity inl lsb 1 k? ?1 0.3 +1 10 k?/50 k?/100 k? ?0.25 0.1 +0.25 full - scale error v wfse code = 0x3f lsb 1 k? ?6 ?3 0 10 k? ?1 ?0.3 0 50 k?/100 k? ?1 ?0.1 0 zero - scale error v wzse code = 0x00 lsb 1 k? ?40c < t a < 85c 0 3 5 lsb 85c < t a < 125c 6 lsb 10 k? ?40c < t a < 85c 0 0.3 1 lsb 85c < t a < 125c 1.5 lsb 50 k?/100 k? 0 0.1 0.5 lsb voltage di vider temperature coefficient ( v w 10 6 )/(v w t) code = 0x00/0x20 120/15 ppm/c resistor terminals voltage range v a , v b ,v w gnd v dd v capacitance a, capacitance b c a , c b f = 1 mhz, measured to gn d , code = 0x20 45 pf capacitance w c w f = 1 mhz, measured to gnd , code = 0x20 60 pf common - mode leakage i cm v a = v b = v dd /2 10 na digital inputs and outputs input logic high v ih 0.7 v l v l + 0.5 v input logic low v il ?0.5 + 0.3 v l v leakage current i il a sda, ad0, ad1 v in = 0 v or 5 v 0.01 1 scl C logic high v in = 0 v ?2.5 ?1.4 +1 scl C logic low v in = 5 v 0.01 1 input capacitance c il 5 pf
ad5258 data sheet rev. d | page 4 of 24 parameter symbol conditions min typ 1 max unit power supplies power supply range v dd 2.7 5.5 v positive supp ly current i dd 0.5 2 a logic supply v logic 2.7 5.5 v logic supply current i logic v ih = 5 v or v il = 0 v ?40c < t a < 85c 3 6 a 85c < t a < 125c 9 a programming mode current (eeprom) i logic(prog) v ih = 5 v or v il = 0 v 35 ma pow er dissipation p diss v ih = 5 v or v il = 0 v, v dd = 5 v 20 40 w power supply rejection ratio psrr v dd = +5 v 10%, code = 0x20 0.01 0.06 %/% dynamic characteristics bandwidth ?3 db bw code = 0x20 r ab = 1 k? 18000 khz r ab = 10 k? 1000 khz r ab = 50 k? 190 khz r ab = 100 k? 100 khz total harmonic distortion thd w r ab = 10 k?, v a = 1 v rms , v b = 0, f = 1 khz 0.1 % v w settling time t s r ab = 10 k?, v ab = 5 v, 1 lsb error band 500 ns resistor noise voltage density e n_ wb r wb = 5 k?, f = 1 khz 9 nv/hz 1 typical values represent average readings at 25c and v dd = 5 v .
data sheet ad5258 rev. d | page 5 of 24 timing characteristi cs v dd = v logic = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +85c, unless otherwise noted. table 2 . parameter symbol conditions min typ max unit i 2 c interfa ce timing characteristics scl clock frequency f scl 0 400 khz t buf bus - free time b etween s top and s tart t 1 1.3 s t hd;sta hold time (repeated start ) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clo ck t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup tim e for repeated s tart condition t 5 0.6 s t hd; dat data hold time t 6 0 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for s top condition t 10 0.6 s eeprom data storing time t eemem_store 26 ms eeprom data restoring time at power on 1 t eemem_restore1 v dd rise time dependant. measure with - o ut dec oupling capacitors at v dd and gnd. 300 s eeprom data restoring time upon restore command 1 t eemem_restore2 v dd = 5 v. 300 s eeprom data rewritable time 2 t eemem_rewrite 540 s flash/ee memory reliability end urance 3 100 700 kcycles data retention 4 100 years 1 during power - up, the output is momentarily preset to midscale before restoring ee pro m content. 2 delay time after power - on p reset prior to writing new ee pro m dat a . 3 endurance is qualified to 10 0,000 cycles per jedec std. 22 method a117 and is measured at ? 40 c, +25 c, and +85 c; typical endurance at +25 c is 700,000 cycles. 4 retention lifetime equivalent at junction temperature (t j ) = 55 c per jedec std. 22, method a117. retention lifetime based on an activation energy of 0.6 ev derates with junction temp erature. 05029-004 t 1 scl sda p s p t 3 t 2 t 8 t 9 t 8 t 9 t 4 t 5 t 7 t 6 t 10 figure 3. i 2 c interface timing diagram
ad5258 data sheet rev. d | page 6 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v dd to gnd ? 0.3 v to +7 v v a , v b , v w to gnd gnd ? 0.3 v, v dd + 0.3 v i max pulsed 1 20 ma continuous 5 ma digital inputs and output voltage to gnd 0 v to 7 v operating temperature range ? 40c to +85c maximum junction temperature (t jmax ) 150c storage temperatur e ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec thermal resistance 2 ja : msop -10 200c/w 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax C t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this i s a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affec t device reliability. esd caution
data sheet ad5258 rev. d | page 7 of 24 pin configuration and fu nction descriptions 05029-005 ad5258 top view (not to scale) w 1 ad0 2 ad1 3 sda 4 scl 5 a b v dd gnd v logic 10 9 8 7 6 figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 w w terminal, gnd v w v dd . 2 ad0 programmable pin 0 for multiple package decoding. state is registered on power-up. 3 ad1 programmable pin 1 for multiple package decoding. state is registered on power-up. 4 sda serial data input/output. 5 scl serial clock input. positive edge triggered. 6 v logic logic power supply. 7 gnd digital ground. 8 v dd positive power supply. 9 b b terminal, gnd v b v dd . 10 a a terminal, gnd v a v dd .
ad5258 data sheet rev. d | page 8 of 24 typical performance characteristics v dd = v logic = 5.5 v, r ab = 10 k ? , t a = 25c, u nless otherwise noted. 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 8 16 24 32 40 48 56 64 05029-006 code (decimal) rheos ta t mode in l (lsb) 5.5v 2.7v figure 5. r - inl vs. code vs. supply voltage s 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 8 16 24 32 40 48 56 64 05029-007 code (decimal) rheos ta t mode dn l (lsb) 5.5v 2.7v figure 6. r - dnl vs. code vs. supply voltages 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 8 16 24 32 40 48 56 64 05029-008 code (decimal) potentiometer mode in l (lsb) ?40c +25oc +85oc figure 7 . inl vs. code vs. temperature 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 8 16 24 32 40 48 56 64 05029-009 code (decimal) potentiometer mode dn l (lsb) ?40c +25c +85c figure 8 . dnl vs. code vs. temperature 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 8 16 24 32 40 48 56 64 5.5v 2.7v 05029-010 code (decimal) potentiometer mode in l (lsb) figure 9 . inl vs. code vs. supply voltages 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 8 16 24 32 40 48 56 64 05029-0 1 1 code (decimal) potentiometer mode dn l (lsb) 5.5v 2.7v figure 10 . dnl vs. code vs. supply voltages
data sheet ad5258 rev. d | page 9 of 24 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 8 16 24 32 40 48 56 64 05029-012 code (decimal) rheos ta t mode in l (lsb) ?40c +25c +85c figure 11 . r - inl vs. code vs. temperature 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 8 16 24 32 40 48 56 64 05029-013 code (decimal) rheos ta t mode dn l (lsb) ?40c +85c +25c figure 12 . r - dnl vs. code vs. temperature 0 ?0.05 ?0.10 ?0.15 ?0.20 ?0.25 ?0.30 ?0.35 ?0.40 ?0.45 ?0.50 ?40 80 60 40 20 0 ?20 05029-014 temper a ture (oc) fse (lsb) fse @ v dd = 2.7v fse @ v dd = 5.5v figure 13 . full - scale error vs. temperature 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 ?40 80 60 40 20 0 ?20 05029-015 temper a ture (c) zse (lsb) zse @ v dd = 2.7v zse @ v dd = 5.5v figure 14 . zero - scale error vs. temperature 1 0.1 ?40 80 60 40 20 0 ?20 05029-016 temper a ture (c) i dd (a) v dd = 5.5v figure 15 . supply current vs. temperature 6 0 1 2 3 4 5 ?40 80 60 40 20 0 ?20 05029-017 temper a ture (c) i logic , logic supp l y current (a) v logic = 5.5v v logic = 2.7v figure 16 . logic supply current vs. temperature vs. v logic
ad5258 data sheet rev. d | page 10 of 24 250 ?150 ?100 ?50 0 50 100 150 200 0 8 16 24 32 40 48 56 64 05029-018 code (decimal) rheos ta t mode tempco (ppm/c) 1k 10k 50k 100k figure 17 . rheostat mode tempco ( r ab 10 6 ) / (r ab ?t) vs. code 120 100 ?20 0 20 40 60 80 0 8 16 24 32 40 48 56 64 05029-019 code (decimal) potentiometer mode tempco (ppm/c) 1k 50k 10k 100k figure 18 . potentiometer mode tempco ( v w 10 6 )/( v w t) vs. code 350 300 0 50 100 150 200 250 ?40 80 60 40 20 0 ?20 05029-020 temper a ture (c) r wb @ 0x00 r wb @ v dd = 2.7v r wb @ v dd = 5.5v figure 19 . r wb vs. temperature 120 100 80 60 40 20 0 ?40 80 60 40 20 0 ?20 05029-021 temper a ture (c) t ot al resis t ance (k) 10k r t @ v dd = 5.5v 1k r t @ v dd = 5.5v 50k r t @ v dd = 5.5v 100k r t @ v dd = 5.5v figure 20 . total resistance vs. tempera ture 05029-022 ?54 ?60 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 10k 100k 1m 10m 100m gain (db) frequenc y (hz) 0x20 0x10 0x08 0x04 0x02 0x01 figure 21 . gain vs. frequency vs. code, r ab = 1 k ? 05029-023 ?54 ?60 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 1k 10k 100k 1m 10m gain (db) frequenc y (hz) 0x20 0x10 0x08 0x04 0x02 0x01 figure 22 . gain vs. frequency vs. code, r ab = 10 k ?
data sheet ad5258 rev. d | page 11 of 24 05029-024 ?54 ?60 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 1k 10k 100k 1m gain (db) frequency (hz) 0x20 0x10 0x08 0x04 0x02 0x01 figure 23. gain vs. frequency vs. code, r ab = 50 k 05029-025 0x20 0x10 0x08 0x04 0x02 0x01 ?54 ?60 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 1k 10k 100k 1m gain (db) frequency (hz) figure 24. gain vs. frequency vs. code, r ab = 100 k 10k 1k 100 10 012345 05029-026 v ih (v) i logic (a) v dd = v logic = 5v v dd = v logic = 3v figure 25. logic supply current vs. input voltage 80 60 40 20 0 100 1k 1m 100k 10k 05029-027 frequency (hz) psrr (db) code = midscale, v a = v logic , v b = 0v psrr @ v logic = 5v dc 10% p-p ac psrr @ v logic = 3v dc 10% p-p ac figure 26. power supply rejection ratio vs. frequency
ad5258 data sheet rev. d | page 12 of 24 05029-028 400ns/div 1 2 v w scl 5v/div 500mv/div figure 27 . digital feedthrough 05029-029 v w 1 1s/div 200mv/div figure 28 . midscale glitch, code 07f to code 080 05029-030 1 2 v w sc l 200ns/div 5v/div 2v/div figure 29 . large - signal settling time
data sheet ad5258 rev. d | page 13 of 24 test circuits figure 30 through figure 35 illustrate the test circuits that define the test conditions used in the product specification tables. 05029-031 v ms a w b dut v+ v+ = v dd 1lsb = v+/2 n figure 30 . test circuit for potentiometer divider nonlinearity error (inl, dnl) 05029-032 no connect i w v ms a w b dut figure 31 . test circuit for resistor position nonlinearity error (rheostat operation; r - inl, r - dnl) 05029-033 v ms2 v ms1 v w a w b dut i w = v dd /r nomina l r w = [v ms1 ? v ms2 ]/i w figure 32 . test circuit for wiper resistance 05029-034 dut a w b v+ v ms % v dd % v dd v a v ms v+ = v dd 10% pssr (%/%) = figure 33 . test circuit for power supply sensitivity (pss, pssr) 05029-035 +5v ?5v w a +2.5v b v out offset gnd dut ad8610 v in figure 34 . test circuit for gain vs. frequency 05029-036 w b dut i sw i sw r sw gnd t o v dd code = 0x00 = 0.1v 0.1v figure 35 . test circuit for common - mode leakage current
ad5258 data sheet rev. d | page 14 of 24 theory of operation the ad5258 is a 64 - position digitally c ontrolled variable resistor (vr) device. the wipers default value prior to pro - gramming the eeprom is midscale. programming the vari able resistor rheostat operation the nominal resistance (r ab ) of the rdac between terminal a and terminal b is available in 1 k?, 10 k?, 50 k?, and 100 k?. the no minal resistance of the vr has 64 contact points access ed by the wiper terminal. the 6 - bit data in the rdac latch is decoded to select one of 64 possible settings. a w b a w b a w b 05029-037 figure 36 . rheostat mode con figuration the general equation determining the digitally programmed output resistance between wiper w and terminal b is ( ) w ab wb r r d d r + = 2 64 (1) where: d is the decimal equivalent of the binary code loaded in the 6 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance contributed by the on resistance of each internal switch. d5 d4 d3 d2 d1 d0 rdac l a tch and decoder r s r s r s r s a w b 05029-038 figure 37 . ad5258 equivalent rdac circuit note that in the zero - scale condition, there is a relatively low value finite wiper resistance. care should be taken to limit the current flow between wiper w and terminal b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or destruction of the internal switch contact may occur. similar to the mech anical potentiometer, the resistance of the rdac between wiper w and terminal a produces a digitally controlled complementary resistance, r wa . the resistance value setting for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is ( ) + ? = 2 64 64 (2) typical device - to - device matching is process lot dependent and may vary by up to 30%. for this reason, resistance tolerance is stored in the eeprom such that the user will know the actual r ab within 0.1%. programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper w - to - terminal b and wiper w - to - terminal a propor - tional to the input vo ltage at terminal a - to - terminal b. unlike the polarity of v dd - to - gnd, which must be posi tive, voltage across terminal a - to - terminal b, wiper w - to - terminal a, and wiper w - to - terminal b can be at either polarity. a v i w b v o 05029-039 figure 38 . potent iometer mode configuration if ignoring the effect of the wiper resistance for approximation, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at wiper w - to - terminal b starting at 0 v up to 1 lsb less than 5 v. the ge neral equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is ( ) 64 64 64 ? + = (3) a more accurate calculation, which includes the effect of wiper resistance ( v w ) is b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = (4) operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of i nternal r esistors ( r wa and r wb ) and n ot the abso - lute values.
data sheet ad5258 rev. d | page 15 of 24 i 2 c interface note that the wipers default value prior to programming the eeprom is midscale. the master initiates a data transfer by establishing a start con - dition when a high - to - low transition on the sda line occurs while scl is high (see figure 3 ). the next byte is the slave address byte, which consists of the slave address (first seven bits) followed by an r/ w bit (see table 6 ) . when the r/ w bit is high, the master reads from the slave device. when the r/ w bit is low, the master writes to the slave device. the slave address of the part is determined by two configurable address pins, ad0 and ad1. the state of the se two pins is regis - tered upon power - up and decoded into a corresponding i 2 c 7 - bit address (see table 5 ). the slave address corresponding to the transmitted address bits responds by pulling the sda line low during the ninth cloc k pulse (this is termed the slave acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. writin g in the write mode, the last bit (r/ w ) of the slave address byte is logic low. the second byte is the instruction byte. the first three bits of the instruction byte are the command bits (see table 6 ). the user must choose whethe r to write to the rdac registe r or eeprom register or to activate the software write protect (see table 7 to table 10 ). the final five bits are all zeros (see table 13 and table 14 ). the slave again responds by pulling the sda line low during the ninth clock pulse. the final byte is the data byte msb first. dont cares can be left either high or low. in the case of the write protect mode, data is not stored; rather, a logic high in the l sb enables write protect. likewise, a logic low disable s write protect. the slave again responds by pulling the sda line low during the ninth clock pulse. storing/restoring in this mode, only the address and instruction bytes are nec - essary. the last bit ( r/ w ) of the address byte is logic low. the first three bits of the instruction byte are the command bits (see table 6 ). the two choices are transfer data from rdac - to - eeprom (store) or from eeprom - to - rdac (r estore). the final five bits are all zeros (see table 13 and table 14). in addition, users should issue a n nop command immediately after restoring the eemem setting to rdac, thereby mini - mizing supply curr ent dissipation. reading assuming the register of interest was not just written to, it is necessary to write a dummy address and instruction byte. the instruction byte will vary depending on whether the data that is wanted is the rdac register, eeprom r egister, or tolerance register (see table 11 to table 16 ). after the dummy address and instruction bytes are sent, a repea t start is necessary. after the repeat start, another address byte is needed, except this time the r/ w bit is logic high. following this address byte is the readback byte containing the informa - tion requested in the instruction byte. read bits appear on the negative edges of the clock. dont cares may be in either a high or low state. the tolerance register can be read back individually (see table 15 ) or consecutively (see table 16 ). refer to the read modes section for detaile d information on the interpreta tion of the tolerance bytes. after all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low - to - high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see table 8 ). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brin gs the sda line low before the 10 th clock pulse and raises sda high to establish a stop conditi on (see table 11). a repeated write function provides the user with the fl exibility of updat ing the rdac output multiple times after add ressing and i nstructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in the write mode, the rdac output is updated on each successive byte until a stop condition is received. if different instruct ions are needed, the write/read mode must re start with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5258 data sheet rev. d | page 16 of 24 i 2 c byte formats the following generic, write, read, and store/restore control regis ters for the ad5258 refer to the device addresses listed in table 5 , and following is the mode/c ondition reference key. ? s = start condition ? p = stop condition ? sa = slave acknowledge ? ma = master acknowledge ? na = no acknowledge ? w = write ? r = read ? x = dont care ? ad1 and ad0 are two - state address pins. table 5 . device address lookup ad1 address pin ad0 address pin i 2 c device address 0 0 0011000 1 0 0011010 0 1 1001100 1 1 1001110 ge neric interface table 6 . generic interface format s 7 - bit device address (see table 5 ) r/ w sa c2 c1 c0 a4 a3 a2 a1 a0 sa d7 d6 d5 d4 d3 d2 d1 d0 sa p slave address byte instruction byte data byte table 7 . rdac -to - eeprom interface command descriptions c2 c1 c0 command description 0 0 0 operation between i 2 c and rdac 0 0 1 operation between i 2 c and eeprom 0 1 0 operation between i 2 c and write protection register. see table 10. 1 0 0 nop 1 0 1 restore eeprom to rdac 1 1 1 0 store rdac to eeprom 1 this command leaves the device in the eemem read power state, which consumes power. issue the nop command to return the devic e to its idle state. write modes table 8 . writing to rdac register s 7 - bit device address (see table 5 ) 0 sa 0 0 0 0 0 0 0 0 sa x x d5 d4 d3 d2 d1 d0 sa p slave address byte instruction byte data byte table 9 . writing to eeprom register s 7 - bit device address (see table 5 ) 0 sa 0 0 1 0 0 0 0 0 sa x x d5 d4 d3 d2 d1 d0 sa p slave address byte instruction byte data byte the wipe rs default value prior to programming the eeprom is midscale. table 10 . activating/deactivating software write protect s 7 - bit device address (see table 5 ) 0 sa 0 1 0 0 0 0 0 0 sa 0 0 0 0 0 0 0 wp sa p slave address byte instruction byte data byte t o activate the write protection mode, the wp bit in table 10 must be logic high. t o deactivate the write protection, the command must be re sent except with the wp in logic zero state.
data sheet ad5258 rev. d | page 17 of 24 read modes read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes tha t funct ion to place the pointer toward the correct register. this is the reason for the repeat start. in theory, this step can be avoided if the user is interested in reading a register that was previously written to. for example, if the eeprom was just wr itten to, the user can skip the two dummy bytes and proceed directly to the slave address byte followed by the eeprom readback data. table 11 . traditional readback of rdac register value s 7 - bit device address (see table 5 ) 0 sa 0 0 0 0 0 0 0 0 sa s 7 - bit device address (see table 5) 1 sa x x d5 d4 d3 d2 d1 d0 na p slave address byte instruction byte slave address byte read -b ack data repeat s tart table 12 . traditional readback of stored eeprom value s 7 - bit device address (see table 5 ) 0 sa 0 0 1 0 0 0 0 0 sa s 7 - bit device address (see table 5 ) 1 sa x x d5 d4 d3 d2 d1 d0 na p slave address byte instruct ion byte slave address byte read -b ack data repeat s tart store/restore modes table 13 . storing rdac value to eeprom s 7 - bit device address (see table 5 ) 0 sa 1 1 0 0 0 0 0 0 sa p slave address byte instruction byte ta ble 14 . restoring eeprom to rdac 1 s 7 - bit device address (see table 5 ) 0 sa 1 0 1 0 0 0 0 0 sa p slave address byte instruction byte 1 user should issue an nop command immediately after this command to conserve power.
ad5258 data sheet rev. d | page 18 of 24 tolerance readback m odes table 15 . traditional readback of toleran ce (individually) s 7 - bit device address (see table 5 ) 0 sa 0 0 1 1 1 1 1 0 sa s 7 - bit device address (see table 5 ) 1 sa d7 d6 d5 d4 d3 d2 d1 d0 na p slave address byte instruction byte slave address byte sign + integer byte repeat s tart s 7 - bit device address (see table 5 ) 0 sa 0 0 1 1 1 1 1 1 sa s 7 - bit device address (see table 5 ) 1 sa d7 d6 d5 d4 d3 d2 d1 d0 na p slave address byte instruction byte slave address byte decimal byte repeat s tart table 16. traditional readback of tolerance (consecutively) s 7 - bit device address (see table 5 ) 0 sa 0 0 1 1 1 1 1 0 sa s 7 - bit device address (see table 5 ) 1 sa d7 d6 d5 d4 d3 d2 d1 d0 ma d7 d6 d5 d4 d3 d2 d1 d0 na p slave address byte i nstruction byte slave address byte sign + integer byte decimal byte 9 repeat s tart calculating r ab tolerance stored in read - only memory 05029-040 a a a d7 d6 d5 d4 d3 d2 d1 d0 sign sign seven bits for an integer number 2 6 2 5 2 4 2 3 2 2 2 1 2 0 d7 d6 d5 d4 d3 d2 d1 d0 eight bits for a decima l number 2 ?8 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 figure 39 . format of stored tolerance in sign magnitude format with bit position descriptions (unit is percent; only data bytes are shown) the ad5258 feature s a patented r ab tolerance storag e in the non volatile memory. t olerance is stored in the memory during factory production and can be read by users at any time. the knowledge of stored tolerance allows users to accurately calcu - late r ab . this feature is va luable for precision, rheostat mode, and open - loop applications where knowledge of absolute resistance is critical. the stored tolerance resides in the read - only memory and is expressed as a percentage. the tolerance is stored in two memory loc ation bytes in sign magnitude binary form (see figure 39 ). the two ee prom address bytes are 11110 (sign + integer) and 11111 (decimal number). the two bytes can be individually accessed with two separate commands (see table 15 ). alternatively, read - back of the first byte followed by the second byte can be done in one command (see table 16 ). in the l atter case, the memory pointer automatically increment s from the first to the second eeprom loca tion (increments from 11110 to 11111) if read consecutively. in the first memory location, the msb is designated for the sign (0 = + and 1 = ? ) and the seven lsbs are designated for the intege r portion of the tolerance. in the second memory location, all eight data bits are designated for the decimal portion of tolerance . note that the decimal portion has a limited accuracy of only 0.1%. for example, if the rated r ab = 10 k? and the data readback from address 1 1110 shows 0001 1100 and from address 11111 sh ows 0000 1111, the tolerance can be calculated as msb: 0 = + next 7 msb: 001 1100 = 28 8 lsb: 0000 1111 = 15 2 C 8 = 0.06 tolerance = 28.06% rounded tolerance = 28.1% and therefore r ab_actual = 12.810 k?
data sheet ad5258 rev. d | page 19 of 24 esd protection of di gital pins and resistor termina ls the ad5258 v dd , v logic , and gnd power supplies define the boundary conditions for proper 3 - terminal and digital input operation. supply signals present on terminal a, terminal b, and terminal w that exceed v dd or gnd are clamped by the internal forward - biased esd protection diodes (see figure 40 ). digital input scl and digital input sda are clamped by esd protection diodes with respect to v logic and gnd as shown in figure 41. gnd a w b v dd 05029-041 figure 40 . maximum terminal voltages set by v dd and gnd 05029-042 g n d sc l sd a v logic figure 41 . maximum terminal voltages set by v logic and gnd power - up sequence because the esd protection diodes limit the voltage compliance at terminal a, terminal b, and term inal w (see figure 40 ), it is important to power gnd/v dd /v logic before applying any volt - age to terminal a, terminal b, and terminal w; otherwise, the diode is forward - biased such that v dd and v logic are powered unintentionally an d may affect the users circuit. the ideal power - up sequence is in the following order: gnd, v dd , v logic , digital inputs, and then v a , v b , v w . the relative order of powering v a , v b , v w and the digital inputs is not important as long as they are powered a fter gnd , v dd , and v logic . layout and power sup ply bypassing it is good practice to employ compact, minimum lead length layout design. the leads to the inputs should be as direct as possible with minimum conductor length. ground paths should have low resi stance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with disc or chip ceramic capaci - tors of 0.01 f to 0.1 f. in addition , l ow esr 1 f to 10 f tantalum or electro lytic capacitors should be applied at the supplies to minimize any transient disturbance and low fre - quency ripple (see figure 42 ). as well, t he digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. v dd gnd v dd c2 10f c1 0.1f ad5258 + 05029-043 figure 42 . power supply bypassing multiple devices on one bus the ad5258 has two configurab le a ddress p ins , ad0 and ad1. the state of these two pins is registered upon power - up and decoded into a corresponding i 2 c - compatible 7 - bit address (see table 5 ). this allows up to four devices on the bus to be written to or read from independently.
ad5258 data sheet rev. d | page 20 of 24 display applications circuitry a special featur e of the ad5258 is its unique separation of the v logic and v dd supply pins. the reason for doing this is to provide greater flexibility in applications that do not always provide the needed supply voltages. in particular, lcd panels often require a v com voltage in the range of 3 v to 5 v. the circuit in figure 43 is the rare exception in which a 5 v supply is available to power the digital potentiometer. 05029-045 a b w r2 10k r1 70k r3 25k v dd v logic scl sda gnd ? + u1 ad8565 3.5v < v com < 4.5v 14.4v vcc (~3.3v) 5v ad5258 mcu c1 1f r5 10k r6 10k figure 43 . v com adjustment application m ore com mon ly, only analog 14.4 v and digital logic 3.3 v sup - plies are available (see figure 44) . by placing discrete resistors above and below the digital pot entiometer , v dd can be tapped off the resistor string itself. based on the cho sen resistor values, the voltage at v dd in this case equals 4.8 v, allowing t he wiper to be safely operated up to 4.8 v. the current draw of v dd will not affect that nodes bias because it is only on the order of microamps. v logic is tied to the microcontr ollers (mcu) 3.3 v digital supply because v logic will draw the 35 ma that is needed when writing to the eeprom. it would be impractical to try to source 35 ma t hrough the 70 k? resistor; therefore, v logic is not connected to the same node as v dd . for this reason, v logic and v dd are provided as two separate supply pins that can either be tied together or treated inde - pendently; v logic supplies the logic/eeprom with power, and v dd biases up the a, b, and w terminals for added flexibility. 05029-046 a b w r2 10k r1 70k r3 25k v dd v logic scl sda gnd ? + u1 ad8565 3.5v < v com < 4.5v 14.4v vcc (~3.3v) ad5258 mcu c1 1f r5 10k r6 10k supplies power t o both the mcu and the logic supp l y of the digi t al potentiometer figure 44 . ci rcuitry when a separate supply i s not available for v dd for a more detailed look at this application, refer to the article, simple v com adjustment uses any logic - supply voltage in the september 30, 2004, issue of edn magazine.
data sheet ad5258 rev. d | page 21 of 24 outl ine dimensions c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 figure 45 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model 1 r ab ( k ? ) temperature range package description 2 package option branding ad5258brmz1 1 ? 40c to +8 5c 10- lead msop rm - 10 d4k ad5258brmz1 -r7 1 ? 40c to +85c 10- lead msop rm - 10 d4k ad5258brmz10 10 ? 40c to +85c 10- lead msop rm - 10 d4l ad5258brmz10 -r7 10 ? 40c to +85c 10- lead msop rm - 10 d4l ad5258brmz50 50 ? 40c to +85c 10 - lead msop rm - 10 d4m ad52 58brmz50 -r7 50 ? 40c to +85c 10- lead msop rm - 10 d4m ad5258brmz100 100 ? 40c to +85c 10- lead msop rm - 10 d4n ad5258brmz100 -r7 100 ? 40c to +85c 10- lead msop rm - 10 d4n eval - ad5258dbz evaluation board 1 z = rohs c ompliant part. 2 the evaluation board is shipped with the 10 k ? r ab resistor option; however, the board is compatible with all available resistor value options.
ad5258 data sheet rev. d | page 22 of 24 notes
data sheet ad5258 rev. d | page 23 of 24 notes
ad5258 data sheet rev. d | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2005 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their re spective owners. d05029 - 0 - 1/13(d)

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